Publications & Works

Articles Published in Journals That Entered SCI, SSCI and AHCI Indexes

Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol.35, no.12, pp.2093-2103, 2016 (Journal Indexed in SCI) identifier identifier

Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol.35, no.1, pp.141-154, 2016 (Journal Indexed in SCI) Creative Commons License identifier identifier

Refereed Congress / Symposium Publications in Proceedings

Small Delay Defect Diagnosis through Failure Observation Ordering


Full Exploitation of Process Variation Space for Continuous Delivery of Optimal Delay Test Quality

18th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 22 - 25 January 2013, pp.552-557 identifier identifier

Tracing the Best Test Mix through Multi-Variate Quality Tracking

IEEE 31st VLSI Test Symposium (VTS), California, United States Of America, 29 April - 02 May 2013 identifier identifier

Delay Test Resource Allocation and Scheduling for Multiple Frequency Domains

30th IEEE VLSI Test Symposium (VTS), Hawaii, United States Of America, 23 - 25 April 2012, pp.114-119 identifier identifier

Adaptive Test Optimization through Real Time Learning of Test Effectiveness

Design, Automation and Test in Europe Conference (DATE), Grenoble, France, 14 - 18 March 2011, pp.1430-1435 identifier identifier

Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost

20th Asian Test Symposium (ATS), New Delhi, India, 20 - 23 November 2011, pp.323-328 identifier identifier

Delay Test Quality Maximization through Process-aware Selection of Test Set Size

IEEE International Conference on Computer Design, Amsterdam, Netherlands, 3 - 06 October 2010, pp.390-395 identifier identifier

Test cost reduction through a reconfigurable scan architecture

35th International Test Conference, Charlottetown, Canada, 26 - 28 October 2004, pp.945-952 identifier identifier

Extending the applicability of parallel-serial scan designs

IEEE International Conference on Computer Design, San-Jose, Costa Rica, 11 - 13 October 2004, pp.200-203 identifier

CircularScan: A scan architecture for test cost reduction

Design, Automation and Test in Europe Conference and Exhibition (DATE 04), Paris, France, 16 - 20 February 2004, pp.1290-1295 identifier identifier

Design space exploration for aggressive test cost reduction in circular scan Architectures

International Conference on Computer Aided Design (ICCAD 2004), San-Jose, Costa Rica, 7 - 11 November 2004, pp.726-731 identifier

Extracting precise diagnosis of bridging faults from stuck-at fault information

12th Asian Test Symposium, Xian, China, 16 - 19 November 2003, pp.230-235 identifier identifier

Fault dictionary size reduction through test response superposition

20th IEEE International Conference on Computer Design, Freiburg, Germany, 16 - 18 September 2002, pp.480-485 identifier