Extending the applicability of parallel-serial scan designs


Arslan B. , Sinanoglu O., Orailoglu A.

IEEE International Conference on Computer Design, San-Jose, Costa Rica, 11 - 13 October 2004, pp.200-203 identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/iccd.2004.1347922
  • City: San-Jose
  • Country: Costa Rica
  • Page Numbers: pp.200-203

Abstract

Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propose two different methodologies for test cost reduction in scan-based designs. The first methodology improves on the Illinois Scan Architecture, aiming at reducing the high test cost of the test vectors that necessitate the serial test application mode. The second methodology employs on-chip serial transformations to generate an input stimulus that can be applied efficiently. The transformation-based methodology utilizes the proposed scan design to obtain the minimal cost input stimulus. The experimental results indicate that a substantial test cost reduction, reaching 90% levels, can be obtained.