Research Information System
Design, Automation and Test in Europe Conference and Exhibition (DATE 04), Paris, France, 16 - 20 February 2004, pp.1290-1295
Scan-based designs are widely used to decrease the complexity of the test generation process; nonetheless, they increase test time and volume. A hew scan architecture is proposed to reduce test time and volume while retaining the original scan input count.. The proposed architecture allows the use of the captured response as a template for the next pattern with only the necessary bits of the captured response being updated while observing the full captured response. The theoretical and experimental analysis promises a substantial reduction in test cost for large circuits.