Delay Test Quality Maximization through Process-aware Selection of Test Set Size


Arslan B. , Orailoglu A.

IEEE International Conference on Computer Design, Amsterdam, Netherlands, 3 - 06 October 2010, pp.390-395 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/iccd.2010.5647687
  • City: Amsterdam
  • Country: Netherlands
  • Page Numbers: pp.390-395

Abstract

The quality of a delay test set hinges not only on test patterns and the distribution of the delay defects but on the variations in process parameters as well. Process variations result in the same delay test set displaying differences from die to die in the detection of particular delay defects at the identical circuit node. The application of an identical test set to all devices independent of process variations consequently results in delivering inefficiencies in test time utilization. This paper proposes a delay test technique that adaptively changes the size of the test set based on the position of the device in the process variation space in order to maximize test quality within a given test time.