Design space exploration for aggressive test cost reduction in circular scan Architectures


Arslan B. , Orailoglu A.

International Conference on Computer Aided Design (ICCAD 2004), San-Jose, Costa Rica, 7 - 11 November 2004, pp.726-731 identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/iccad.2004.1382671
  • City: San-Jose
  • Country: Costa Rica
  • Page Numbers: pp.726-731

Abstract

Scan-based designs effectively reduce test generation complexity and thus deliver improved fault coverage. Nevertheless, the traditional scan architectures suffer from increased test time and test data volume. The CircularScan architecture [1] provides a flexible environment for test cost reduction. The new scan design enables the use of the captured response of the previously applied test pattern as a template. The subsequent pattern is loaded by efficiently performing the necessary changes on the template through the functionality provided by the new architecture, conceptually exploiting the inherent low specified bit density of the test patterns. We explore the space of possible design alternatives built on the CircularScan architecture; the design alternatives are presented with accompanying test application methods. The experimental results indicate a substantial test cost reduction, reaching 90% levels. The proposed scheme is not only easily scalable but also promises further reductions in test cost when applied to large state of the art ICs.